To determine whether semiconductor devices have manufacturing defects, such devices are tested. Typically, an automatic test system having a test head is used to transmit appropriate signals to and receive signals from the device under test (DUT). Depending upon the stage in the manufacturing cycle, a device handler or a wafer prober may be used to automatically bring each device in turn into a position to be tested. The test head is docked with the wafer prober or device handler, and an interface unit is provided to convey the signals between the DUT and the test head.
In performing such tests, it is common for the test head to both transmit and receive signals that have low signal levels and high frequencies. Further, with increasing complexity of devices under test, the density of signal connections between the test head and the DUT similarly increases.
Thus, it is useful to provide a structure which provides sufficient shielding of signals flowing between the test head and the device handler.
Various devices are known in the prior art to provide shielding between the test head and the device handler. U.S. Pat. No. 6,037,787 (Corwith) discloses a probe interface which is formed from a plurality of metal tubes. The tubes are placed between insulative retainers. Furthermore, U.S. Pat. No. 4,724,180 (Kern) discloses an interface device in which channels are formed therein, and the entire device is coated with a nickel coating. It is desirable to insert conducting structures (such as pogo pin structures) in the channels disclosed in each respective patent. It also desirable, however, for certain conducting structures to not be in contact with the conductive layers. Thus, additional manufacturing steps are performed. Specifically, insulating layers (or spacers) may be needed about the conducting structures to prevent them from coming into contact with conductive members within the channels.